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This is the complete list of references as it appears in the Online TDR. Links to online versions of documents are given wherever possible.
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[1] O. Callot et al., “Experience with the ALEPH Online system”, ALEPH PUB 2001-003, June 2001.
[3] RD-12 Documentation [online] http://www.cern.ch/TTC/intro.html and references therein.
[4] JCOP [online] http://itcowww.cern.ch/jcop/subprojects/Framework/welcome.html
[5] PVSS [online] http://www.pvss.com/english/index.htm
[6] LHCb Front-End Architecture [online] http://lhcb-elec.web.cern.ch/lhcb-elec/html/architecture.htm
[7] R. Jacobsson, “How can I run my Detector”, LHCb 2001-140 DAQ.
[8] R. Jacobsson and B. Jost, “Timing and Fast Control”, LHCb 2001-016 DAQ.
[9] C. Gaspar, R. Jacobsson and B. Jost, “Partitioning in LHCb”, LHCb 2001‑116 DAQ.
[10] J. Christiansen, “Requirements to the L0 front-end electronics”, LHCb 2001‑14
[11] R. Jacobsson, B. Jost and Z. Guzik, “TFC Switch Specifications”, LHCb 2001-018 DAQ.
[14] J. Harvey, “Computing Model – Baseline model of LHCb’s distributed computing facilities," Draft, [online] http://lhcb-comp.web.cern.ch/lhcb-comp/computingmodel/ComputingModelV3.pdf
[16] I. Garcia and J. Christiansen, “Simulation of the L0 front-end electronics,” LHCb 1999-047.
[17] P. Vasquez and J. Christiansen, “Simulation of the LHCb L1 front-end,” LHCb 2001-126.
[18]
R. Jacobsson, “Experience with the TFC Switch – Prototype 1,”
[online]
http://lhcb‑comp.web.cern.ch/lhcbcomp/DAQ/TFC/documents/switch_experience.pdf,
June 2001.
[19] Nick Ellis and John Dawson, private communications.
[20] H. Müller et al., “Readout Unit, FPGA version for link multipexers, DAQ and VELO trigger,” LHCb note Draft [online] http://hmuller.home.cern.ch/hmuller/RU/LHCbNote.pdf
[21] B. Jost et al. "The LHCb Trigger and Data Acquisition System," IEEE Real Time Conference June 14-18, 1999 Santa Fe.
[22] LHCb Level-1 Vertex Topology Trigger, LHCb 1999-31.
[23] J-P. Dufey et al., “Event-building in an intelligent Network Interface Card for the LHCB DAQ,” LHCb 2001-094.
[26] A. Walsch, “A Hardware/Software Triggered DMA Engine,” LHCb 2001-125.
[27] A. Guirao et al., “A networked mezzanine card Linux processor,” in Proc. 12th Real Time Congress on Nucl. and Plasma Sciences, Valencia June 2001, p 81 ff.
[28] J. Toledo, H. Müller, F. Bal and B. Jost, “Readout Unit for the LHCb experiment," Fifth Workshop on Electronics for LHC experiments. Snowmass, Colorado. Sept. 1999
[29] J. Toledo et al., “A Readout Unit for high rate applications,” in Proc. 12th Real Time Congress on Nucl. and Plasma Sciences, Valencia June 2001, p. 230 ff., to appear in IEEE Trans. Nucl. Sci.
[30] W. Bux et al., “Technologies and Building Blocks for Fast Packet Forwarding,” IEEE Commun. Mag., Jan. 2001.
[31] Network Processor Central, [online] http://www.linleygroup.com/npu/
[32] B. Jost and N. Neufeld, “A versatile Network Processor based electronics module for the LHCb Data Acquisition System,” LHCb 2001-132
[33]
IBM PowerNP documentation [online]
http://www-3.ibm.com/chips/techlib/techlib.nsf/products/IBM_PowerNP_NP4GS3
[34]
IBM PowerNP Reference Platform [online]
http://www-3-.ibm.com/chips/techlib/techlib.nsf/products/IBM_PowerNP_NP4GS3_Reference_Platform
[37] OPC foundation, [online] http://www.opcfoundation.org/
[38] W. Salter (ed.), “JCOP Architecture Working Group, “Framework Design Proposal,” CERN-JCOP-2000-007, October 2001, [online] http://itcowww.cern.ch/jcop/subprojects/Architecture/Framework/AWGReport.pdf
[39] LHC Data Interchange WG, “User Requirements,” Report_0600, June 2000, http://wwwlhc.cern.ch/Controls/WG/LDIWG/Report0600.PDF
[40] D. Breton and Ph. Cros, “Serial Protocol for the Experiment Control System of LHCb,” LHCb 2001-144, July 2001, [online] http://www.lal.in2p3.fr/technique/se/pub/lhcb/PCItoSPECS/SPECS.pdf
[41] See e.g. http://atlasinfo.cern.ch/ATLAS/GROUPS/DAQTRIG/DCS/ELMB/elmb.html and links therein.
[42] C. Gaspar, B. Jost, N. Neufeld and S. M. Schmeling, “The Use of Credit Card-sized PCs for interfacing electronics boards to the LHCb ECS,” LHCb 2001-147
[43] Conditions Database see e.g. http://wwwinfo.cern.ch/db/objectivity/docs/conditionsdb/ and references therein.
[44] See e.g. http://lhcb-comp.web.cern.ch/lhcb-comp/ECS/pdf/mccontrol_report.pdf
[46] Moore’s Law at Intel, http://www.intel.com/research/silicon/mooreslaw.htm
[48]
Network Technology Tracking Team (NT3) Report 1999
[online]
http://it-div-cs.web.cern.ch/it-div-cs/public/studies/nt3/nt3-1999.html
[50] Myricom [online] http://www.myri.com/
[52] Ch. E. Spurgeon, Ethernet – The Definitive Guide, O’Reilly & Associates, Sebastopol, 2000
[54] See http://www.oti.net/Systems/Foundry/PDF/big_iron.pdf for more details
[58] C. Bizeau et al., “RD31 Status Report ’97,” CERN/LHCC/97-05
[59] N. Neufeld, “Implementation of the Event Filter Farm CPU node”, LHCb 2001-143
[60] RLX System 324, [online] http://www.rlxtechnologies.com/home.html
[62] I. Pratt and K. Fraser, “Arsenic: a User-accessible Gigabit Ethernet Interface,” Presented at IEEE INFOCOM 2001. [online] Available: http://infocom.ucsd.edu/papers/394-3981268191.pdf
[66] Prizma, [online] http://www.zurich.ibm.com/cs/powerprs.html and references therein.
[67] CERN ECP/FEX: CASCADE User’s Guide, CERN, Geneva, 1997
[68]
S. Schmeling, “LHCb Testbeam DAQ and Controls Support,”
[online]. Available:
http://cern.ch/LHCb-Testbeam
[69] S. Schmeling and R. Beneyton, “LHCb Testbeam 101,” LHCb‑2001‑111
This page last edited by NN on December 18, 2001 |